This invention relates to methods for processing semiconductor devices and more particularly to a method for forming a substantially planar inorganic dielectric layer for use in multilevel semiconductor devices.
In constructing multi-level semiconductor devices, it is necessary to provide an insulating layer between each layer of electrically conducting interconnects. Each dielectric layer must be substantially planar and continuous, that is without cracks or voids, in order to enhance the formation of subsequent interconnect layers and to provide high dielectric integrity between such conductive layers. In addition to promoting continuity in the overlying second metal layer, a planarized dielectric enables the formation of very fine photolithographic patterns to define interconnect layouts with extreme precision. Modern exposure equipment typically comprise projection type printers with a very narrow focusing depth of field. Consequently, any deviation from planarity throws the pattern out of focus and results in poor definition.
In the prior art, insulating layers made from organosilicates, were spun onto the semiconductor device then heated to remove the solvent and form a silicon dioxide type glass. The problem with such prior art technology is that the silicon dioxide layers formed by organosilicate decomposition typically have low dielectric integrity. Furthermore, the maximum thickness to which such materials can be formed by a spin-on process, which process enhances the planarization of the surface of such layers, is approximately 6,000.ANG. and on difficult geometries, substantially less. Spinning on layers having greater thicknesses would result in cracks and crazing, thereby decreasing the integrity of the dielectric layer.
For example, prior art silicon dioxide films formed from solutions of silicon alkoxides, such as tetraethylorthosilane (TEOS), have fairly good dielectric integrity when they are continuous. Such continuity reliably occurs only when these films are applied over substantially flat, unpatterned substrates. When applied over patterned wafers, such films are prone to severe cracking; therefore, film thicknesses in excess of 2,000 to 3000.ANG. are not satisfactory. The problem worsens when the patterned wafer includes areas of widely differing thermal expansion, such as aluminum metallization atop a silicon wafer. In such cases, films of 2,000 to 3,000.ANG. have proven quite unreliable, especially when subjected to temperature excursions typically encountered in subsequent processing.